`timescale 1us/1us
module fsm1_tb ();
    reg clk;
    reg reset;
    wire led;
    fsm1 fsm1(
        .clk(clk),
        .reset(reset),
        .led(led)
    ); 
    defparam fsm1.hightime=25-1;
    defparam fsm1.lowtime=75-1;


    initial begin
                clk<=0;
                reset<=0;
        #20     reset<=1;
        #5000   $stop;     
    end

    always #1 clk<=~clk;
endmodule
